The goal of Technology & Design Kit for Printed Electronics (TDK4PE) is to set a fundamental change in the way printed electronics (PE) are designed and manufactured in Europe, with the aim of reducing costs and time-to-market by more than an order of magnitude for more complex designs than ever before by addressing thousands of transistors on a substrate.
The key is to develop a methodology to enable application-specific PE circuit implementation. This will be achieved by adopting a methodology similar to the silicon microelectronics one: using a Technology and Design Kit (TDK) to abstract physics to a point where engineers could address physical design with sufficient certainty and great freedom for creativity. This TDK will support circuit design at physical, full-custom, and cell-based levels.
TDK4PE addresses the whole product and value chain from concept application to material, through design to manufacturing using Sheet to Sheet (S2S) and analysing the up-scaling to Roll-to-Roll (R2R) processes. It will establish cell-based design methodologies coupled with technology process flows and supported by Electronic Design Automation (EDA) tools towards mass production. EDA needs building cell libraries based on characterized devices made of functional inks and will enable automatic synthesis of circuits with predictable properties, high yield and improved circuit reliability.
Establishing such a methodology is an ambitious task that can only be approached from a consortium possessing a wide range of complementary skills. TDK4PE has brought together such a collaboration of European key players in the fields of materials, inks, printing technologies, manufacturing, modelling, component and system design, microelectronics, EDA tools and applications.
Two key points are at the technological opposite poles of this project, FOLAE technology and applications that shall come together on a seamless way by means of a TDK and its related methodology, which will be the enablers for PE design activities between both of them. This convergence between PE technology and its potential applications will contribute to create a sustainable business sector with potential for significant future growth.
From the start of the project (Oct-2011) till the end of the project (September-2014), the TDK4PE project has defined and developed the methodology and design tool flow. Additionally to the execution of the Project Communication plan to promote the visibility of TDK4PE project within EU and abroad, major progresses during this period have occurred in both technology (process) and EDA as we summarise:
- Definition of a XML capture for a Printed Electronic technology
- Validated with 3 different processes oriented to the implementation of OTFTs: (i) the TDK4PE fully inkjet process, (ii) the CPI evaporation process and (iii) the CSEM gravure printing.
- Guide for the Technology and Design Kit (TDK):
- Definition of Printed Electronics design flows for
- Full-custom physical
- Cell/device based design flow
- Definition of Backend interface from geometrical layout to printable files
- Design flow definition using
- Commercial EDA available tools
- Open/Free domain EDA tools
- Requirements of TDK information for PE design flows
- Basic technology information
- Printing level layout information
- Physical design level information: geometric design layers and design rules, layout extraction rules for LVS comparison, electrical and physical design guidelines.
- Cell libraries and structure for technology independent (pameterisable) levels of abstraction
- The specification of the API for Printed Electronics design flow implementation has been defined.
- Implementations of design kits for CleWin/MaskEngineer and Glade including schematic entry, spice simulation (linking to NGspice, AIMspice and LTspice simulators), layout editors, DRC, XTR, LVS and back-end tools for the TDK4PE project inkjet printed technology, and specific implementations for CPI and CSEM processes.
- Portability to 3rt party technological processes (CSEM for gravure and CPI for evaporation) allowed demonstrating the information exchange methodology to produce design kits and a design guide for those processes and the validation of the design process concerning fabricated devices.
- Therefore, 3 different design kits for inkjet (internal), gravure and evaporation (external) organic electronics processes are being used. This shows the success of the TDK4PE approach and its portability to other PE processes and the advantages towards the virtual foundry concept (through interproject collaboration, in this case with the COLAE project).
- Main efforts in technology have been focussed to optimize the technology used for this project for inkjet printing on S2S, up-scaling fabrication from laboratory based printed to a high productive platforms (DMP3000) using similar set-up that the one required by roll-to-roll machinery (looking at its portability to R2R).
- A very large amount of devices has been fabricated and characterized, making intensive use of a semi-automatic characterization procedure to extract devices behaviour of devices and cells (resistors, capacitors, diodes and OTFTs) and perform tests on DRC structures to optimize fabrication yield versus device and interconnection density. Other structures like RF elements and digital cells and structures have been tested using probe station facilities. Many test benches for OTFTs have been checked allowing in depth analysis and characterization of the devices printed using the large productivity printer DMP3000. Major effort was driven to achieve good quality, high yield and reduced variability for ink-jet based OTFTs.
- Several strategies have been used to increase the yield of transistors implemented using full-inkjet technology concerning materials selection, drop spacing deposition, curing and also fixing the geometrical structure or template proving the dielectric layer as the most critical element.
- Multi-project foil (MPF) strategy allowed the consortium the integration of different designs coming from different partners to be fabricated on common substrates, once fabricated being distributed for its analysis and characterization and modelling.
- For OTFTs, the consortium closed the loop required for an efficient design-technology methodology, composed of: OTFT manufacturing, characterization, semi-physical model adaptation, parameter extraction, Verilog-A model generation, integration in simulators and circuit simulation of new circuits.
- UCM semi-physical models have been selected as the reference models to be integrated in the design framework. Semi-physical models have also been used to model OTFT width and length dependencies.
- Textile piezo-resistor devices have been implemented, characterized and modelled showing good linearity. Two-dimensional arrays of textile devices have been fabricated as a part of the demonstrators.
- Parameterisable cells (pCells) were generated to increase the design productivity. Using pCells, large arrays of similar structures can be built automatically. pCells have been used to generate test structures on individual devices (resistors, capacitors, transistors), structures (logic cells, gate array cells) for obtaining design rules and regular functional structures such as the inkjet gate arrays. pCells have also been ported to CSEM and CPI technologies.
- These IGA structures use a restricted set of transistors sizes (2) according to the ratioed logic topology.
- pCell devices and digital cells have been designed using both design frameworks (Clewin/MaskEngineer and open-source) for the three different technological processes (inkjet, gravure and evaporation).
- A standard cell library has been designed for the CPI process containing a basic set of gates: inverter, nand/nor 2/3.
- The Inkjet Gate Array structure has been proposed in order to implement circuits composed of OTFT arrays with the aim of producing high yield foils out of mid-high yield OTFTs (in these foils). Initial designs show a good equilibrium between OTFT and wiring occupation. For CPI process, 1 IGA structure has been designed containing 1280 OTFTs and 56 I/O pads in 1.5cm x 1.5cm. Different technologies can be used for the functional personalization of the gate-array: Super-fine inkjet (SIJ) and aerosol technologies for digital printing, a mask-based solution and selective laser-ablation. These IGA structures use a restricted set of transistors sizes (2) according to the ratioed logic topology.
- Two demonstrators have been specified and prototyped:
- An RFID tag (antenna, diode and capacitor). All devices were implemented with the required performance.
- A complex flexible sensor-processing-actuator system to implement the Tic-Tac-Toe game, including both textile and plastic components. A complete circuit (147 OTFTs and 30 I/O pads) has been designed using our own standard cell library and was fabricated at CPI.
- A training course has been organized in cooperation with the COLAE project learning strategy that had 12 participants (6 from industry) in its first edition. Design and technology methodologies were demonstrated with the corresponding hand-on with the design tools and a demonstration of fabrication, analysis and characterization facilities.
Next figure shows the EDA tools structure that supports our design methodology. For each of the elementary design steps there is an API that links to each technology data base that supports every foundry design kit. TDK4PE information structure (managed using XML descriptors) is following with the OpenAccess standard from the silicon industry and PDAFlow promoted by Phoenix SoftwareTM.
The effort carried out from May-2014 till September-2014 allowed us to demonstrate (i) how devices can be produced to meet the requirements of the proposed Tic-Tac-Toe demonstrator (technology) and (ii) how the loop technology-tools-design is closed to be able to release a design kit.
A convergent approach has been followed for the fabrication of fully inkjet-printed transistors starting from the specifications of the expected circuit demonstrators transformed into requirements for the inverters and elementary logic gates. This process ends-up by fixing the fabrication recipe for each deposited layer of the fully inkjet-printed devices. Furthermore, the manufacturing process was up-scaled from laboratory printing platforms to industrial printing platforms. This allowed us to increase the throughput remarkably. As result, we investigated the yield and variability of the manufactured devices. In summary, more than 50.000 thin film transistors were manufactured in a sheet-to-sheet process during the project duration. In addition to transistors, also resistors, capacitors, diodes and antennas were considered and produced by inkjet printing. All the devices were characterized concerning their electrical performance and their yield and variability.
Concerning design, the arrays of transistors implemented in our process and in CPI technology have been characterized and new models were generated. Those new device models allowed the project partners to identify combinations of transistors suitable to implement logic gates.
Silver inkjet printing on top of the CPI transistor arrays allowed the consortium (i) to validate this technology as a wiring option and (ii) obtain functional inverters. These functional inverters have been measured, their DC characteristics showing acceptable results (dynamic range of 22.7V for 30V power supply). Also the transient analysis shows results that are consistent with the requirements of the demonstrator (around 250 us propagation delay for 20%-80% range).
Concerning the demonstrators: (i) a hybrid prototype for the RF tag that includes a multi-layer printed antenna printed capacitors and diodes have been implemented where Schottky diodes can rectify signals at 13.56 MHz, and (ii) the tic-tac-toe game implementation has a textile version of the 2-players pressure sensor and the LED array, both implemented by Sensing Tex. Prototypes of the circuit controlling them are being implemented using CPI technology.