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Global project progress

From the start of the project (Oct-2011) till (Oct-2013), the TDK4PE project has defined partially the methodology and design tool flow will develop during the lifetime of this project. Additionally to the definition of the Project Communication plan to promote the visibility of TDK4PE project within EU, major progresses during this period have occurred in both technology (process) and EDA as we summarise:

  • Definition of a XML capture for a Printed Electronic technology


  • Initial guide for the Technology and Design Kit (TDK):
    • Definition of Printed Electronics full-custom physical design flow
    • Definition of Printed Electronics for cell/device based design flow
    • Definition of Backend interface from geometrical layout to printable files
    • Design flow definition using Commercial EDA available tools
    • Design flow definition using Open/Free domain EDA tools
    • Requirements of TDK information for PE design flows
    • Basic technology information
    • Printing level layout information 
    • Physical design level information: geometric design layers and design rules, layout extraction rules for LVS comparison, electrical and physical design guidelines.
    • Cell libraries level for upper level of abstraction

  • Also the specification of the API for Printed Electronics design flow implementation has been defined. Next figure summaries the TDK4PE tools, flows and information bind using the API.

  • Early implementations of design kits for CleWin/MaskEngineer and Glade including schematic entry, NGspice simulation, layout editors, DRC, XTR, LVS and back-end tools for the TDK4PE project inkjet printed technology. In addition, portability to other to external technological processes is being ported, what will further validate our approach.

  • Respect to technology there are special efforts (on-going task) to optimize the technology used for this project for inkjet printing on S2S (looking at its portability to R2R). Due to the amount of devices to be characterized, partners set up a semi-automatic characterization procedure (manual initial placement in the array plus further automatic repetitive placement and data capture) to speed up tests for the expected runs for devices and cells (resistors, capacitors, diodes, inductances, OTFT, pads and cell libraries). Many test benches for resistors and OTFTs have been checked what allows an in depth analysis and characterization of the devices printed using the large productivity printer DMP3000. Major effort is driven to achieve good quality and yield for ink-jet based OTFTs.

  • For OTFTs, we completed the loop required for an efficient design-technology methodology, composed of: OTFT manufacturing, characterization, parameter extraction, Verilog-A model generation, integration in simulators and circuit simulation.

  • UCM semi-physical models have been selected as the reference models to be integrated in the design framework, though the physical model integration tools that is able to add mathematical functions to adjust curves and minimize errors.

  • The Inkjet Gate Array structure has been proposed in order to implement circuits out of OTFT arrays with the aim of producing high yield foils out of mid-high yield OTFTs (in these foils). Initial designs show a good equilibrium between OTFT and wiring occupation. 

  • These IGA structures use only a restricted set of transistors sizes (probably just 2) according to different topologies, what allows an easier method for coping with OTFT variability, that will be analysed through statistical simulation using Monte Carlo Analysis on two different OTFT models (one per OTFT).

  • Two demonstrators have been specified and prototyped with independent components: an RFID tag and a complex flexible sensor-processing-actuator system conceived as an interactive pillow, including both textile and plastic components. This last complex system has been prototyped using FPGAs in order to cope with the flexibility given by high level specifications and to be able to scale the final version depending on the technology results and yield.


Next figure shows the EDA tools structure that will support our proposed design methodology, for each of the elementary design steps, the proposed API with the technological data bases that will support each foundry design kit.


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Dr. Radut Consulting